基于FPGA的彩灯控制器Verilog开发

31
五月
2021

显示部分的参考代码

(末尾附文件)

module Show(
	input 	clk,
	input	reset_n,	
	input 	clk_div,
	
	input 	[31:0] led_mode1,
	input 	[31:0] led_mode2,
	input 	[31:0] led_mode3,
	input 	[31:0] led_mode4,
	input 	[31:0] led_mode5,
	input 	[31:0] led_mode6,
	input 	[31:0] led_mode7,
	input 	[31:0] led_mode8,
	
	input  	sel_a,
	input  	sel_b,
	input  	sel_c,
	
	output	[31:0] led,
	
	output [7:0] mode_db,
	output [7:0] time_l_db,
	output [7:0] time_h_db
);

reg [3:0] s_l;
reg [3:0] s_h;

reg [7:0] time_l_db_r;
reg [7:0] time_h_db_r;
	
reg [31:0] led_r;
reg [7:0] mode_db_r;
wire [2:0] sel;

assign sel = {sel_c,sel_b,sel_a};

always@(posedge clk_div or negedge reset_n)
begin
	if(~reset_n) begin
		s_l <= 4'd0;
		s_h <= 4'd0;
	end
	else begin
		if(s_l < 4'd9)
			s_l <= s_l + 1'b1;
		else begin
			s_l <= 4'd0;
			if(s_h < 4'd9)
				s_h <= s_h + 1'b1;
			else begin
				s_l <= 4'd0;
				s_h <= 4'd0;
			end
		end
	end
end	
	
always@(posedge clk or negedge reset_n)
begin
	if(~reset_n) 
		led_r <= 8'b00000000;
	else begin
		case(sel)
			3'b000:	led_r <= led_mode8;
			3'b001:	led_r <= led_mode1;
			3'b010:	led_r <= led_mode2;
			3'b011:	led_r <= led_mode3;
			3'b100:	led_r <= led_mode4;
			3'b101:	led_r <= led_mode5;
			3'b110:	led_r <= led_mode6;
			3'b111:	led_r <= led_mode7;
			default: led_r <= 8'b00000000;
		endcase
	end
end

always@(posedge clk or negedge reset_n)
begin
	if(~reset_n) 
		mode_db_r <= 8'b00000000;
	else begin
		case(sel)
			3'b000:	mode_db_r <= 8'h01;
			3'b001:	mode_db_r <= 8'h02;
			3'b010:	mode_db_r <= 8'h03;
			3'b011:	mode_db_r <= 8'h04;
			3'b100:	mode_db_r <= 8'h05;
			3'b101:	mode_db_r <= 8'h06;
			3'b110:	mode_db_r <= 8'h07;
			3'b111:	mode_db_r <= 8'h08;
			default: mode_db_r <= 8'b00000000;
		endcase
	end
end

always@(posedge clk or negedge reset_n)
begin
	if(~reset_n) 
		time_l_db_r <= 8'b00000000;
	else begin
		case(s_l)
			4'd0:	time_l_db_r <= 8'h00;
			4'd1:	time_l_db_r <= 8'h01;
			4'd2:	time_l_db_r <= 8'h02;
			4'd3:	time_l_db_r <= 8'h03;
			4'd4:	time_l_db_r <= 8'h04;
			4'd5:	time_l_db_r <= 8'h05;
			4'd6:	time_l_db_r <= 8'h06;
			4'd7:	time_l_db_r <= 8'h07;
			4'd8:	time_l_db_r <= 8'h08;
			4'd9:	time_l_db_r <= 8'h09;
			default: time_l_db_r <= 8'b00000000;
		endcase
	end
end

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