FPGA 外置Flash的读写，用户数据存储

FPGA 外置Flash的读写用户数据存储前言一该功能验证平台及参考文章1Xilinx xc7k325tffg676-22vivado 2017.43验证的flash芯片MT25QL2564参考文章MT25QL256_datasheet5工程网盘链接https://pan.baidu.com/s/1HCBXLYvVRce5k5N_ro-3CA 提取码cyfo二、实现的功能1read Device ID2设置4-byte模式3flash的数据读写三部分代码总结前言大多数FPGA内部不具有掉电存储程序的功能所以都是外置flash存储器来存储程序上电后加载flash中的程序到FPGA中在运行。外置flash不仅可以作为存储程序使用也可以存储任何你想存储的用户数据这样可以更有效的利用flash的存储空间本文不讲其寄存器及原理这个网上很多。一该功能验证平台及参考文章1Xilinx xc7k325tffg676-22vivado 2017.43验证的flash芯片MT25QL2564参考文章MT25QL256_datasheet5工程网盘链接https://pan.baidu.com/s/1HCBXLYvVRce5k5N_ro-3CA 提取码cyfo二、实现的功能1read Device ID2设置4-byte模式3flash的数据读写三部分代码flash_spitimescale1ns/1ps//////////////////////////////////////////////////////////////////////////////////// Company:// Engineer: QSJ//// Create Date: 2021/03/26 9:02:44// Design Name:// Module Name: flash_spi// Project Name:// Target Devices:// Tool Versions:// Description://// Dependencies://// Revision:// Revision 0.01 - File Created// Additional Comments:////////////////////////////////////////////////////////////////////////////////////moduleflash_spi(input wire sys_clk,input wire i_rst_n,// ---------- spi port ---------output wire o_spi_clk,output wire o_spi_cs,output wire o_spi_mosi,input wire i_spi_miso,// --------- data port -----------input wire[7:0]iv_write_data,output reg o_wr_1_byte_ok,input wire[15:0]iv_write_num,input wire[15:0]iv_read_num,input wire[3:0]iv_cmd_type,output reg o_flash_done,input wire[7:0]iv_flash_cmd,input wire[31:0]iv_flash_addr,output reg[7:0]ov_read_data,output wire o_read_data_vld);wire spi_clk;reg spi_cs;reg spi_mosi;wire spi_miso;assign o_spi_clkspi_clk;assign o_spi_csspi_cs;assign o_spi_mosispi_mosi;assign spi_misoi_spi_miso;reg read_data_vld;reg[7:0]read_data;reg[2:0]spi_state;reg spi_clk_en1b0;reg data_come;assign o_read_data_vldread_data_vld;assign spi_clkspi_clk_en?sys_clk:0;parameter IDLE3b000;parameter CMD_SEND3b001;parameter ADDRESS_SEND3b010;parameter READ_WAIT3b011;parameter WRITE_DATA3b101;parameter FINISH_DONE3b110;reg[7:0]cmd_reg;reg[31:0]address_reg;reg[7:0]wr_bit_cnt;reg[15:0]write_cnt;reg[7:0]rd_bit_cnt;reg[15:0]read_cnt;reg[15:0]read_num_inner;reg read_finish;always (negedge sys_clk)beginif(!i_rst_n)begin spi_cs1b1;spi_stateIDLE;cmd_reg0;address_reg0;spi_clk_en1b0;wr_bit_cnt0;write_cnt0;read_num_inner0;o_flash_done1b0;data_come1b0;o_wr_1_byte_ok1b0;endelsebegincase(spi_state)IDLE:begin spi_clk_en1b0;spi_cs1b1;spi_mosi1b1;cmd_regiv_flash_cmd;address_regiv_flash_addr;o_flash_done1b0;if(iv_cmd_type[3]1b1)begin spi_stateCMD_SEND;wr_bit_cnt7;write_cnt0;read_num_inner0;end end CMD_SEND:begin spi_clk_en1b1;spi_cs1b0;if(wr_bit_cnt0)begin spi_mosicmd_reg[wr_bit_cnt];wr_bit_cntwr_bit_cnt-1b1;endelsebegin spi_mosicmd_reg[0];if((iv_cmd_type[2:0]3b001) | (iv_cmd_type[2:0]3b100))begin spi_stateFINISH_DONE;endelseif(iv_cmd_type[2:0]3b011)begin spi_stateREAD_WAIT;wr_bit_cnt7;read_num_inner1;endelseif(iv_cmd_type[2:0]3b000)begin spi_stateREAD_WAIT;wr_bit_cnt7;read_num_inner17;endelsebegin spi_stateADDRESS_SEND;wr_bit_cnt31;end end end ADDRESS_SEND:beginif(wr_bit_cnt0)begin spi_mosiaddress_reg[wr_bit_cnt];wr_bit_cntwr_bit_cnt-1;endelsebegin spi_mosiaddress_reg[0];if(iv_cmd_type[2:0]3b010)begin spi_stateFINISH_DONE;endelseif(iv_cmd_type[2:0]3b101)begin spi_stateWRITE_DATA;wr_bit_cnt7;endelsebegin spi_stateREAD_WAIT;read_num_inneriv_read_num;end end end READ_WAIT:beginif(read_finish)begin spi_stateFINISH_DONE;data_come1b0;endelsedata_come1b1;end WRITE_DATA:beginif(write_cntiv_write_num)beginif(wr_bit_cnt0)begin spi_mosiiv_write_data[wr_bit_cnt];wr_bit_cntwr_bit_cnt-1b1;o_wr_1_byte_ok1b0;endelsebegin spi_mosiiv_write_data[0];wr_bit_cnt7;o_wr_1_byte_ok1b1;write_cntwrite_cnt1b1;end endelsebegin spi_stateFINISH_DONE;spi_clk_en1b0;o_wr_1_byte_ok1b0;write_cnt0;end end FINISH_DONE:begin spi_cs1b1;spi_mosi1b1;spi_clk_en1b0;o_flash_done1b1;spi_stateIDLE;enddefault:spi_stateIDLE;endcase end end always (posedge sys_clk)beginif(!i_rst_n)begin read_cnt0;rd_bit_cnt0;read_finish1b0;read_data_vld1b0;read_data0;ov_read_data0;endelseif(data_come)beginif(read_cntread_num_inner)beginif(rd_bit_cnt7)begin read_data_vld1b0;read_data{read_data[6:0],spi_miso};rd_bit_cntrd_bit_cnt1b1;endelsebegin read_data_vld1b1;ov_read_data{read_data[6:0],spi_miso};rd_bit_cnt0;read_cntread_cnt1b1;end endelsebegin read_cnt0;read_finish1b1;read_data_vld1b0;end endelsebegin read_cnt0;rd_bit_cnt0;read_finish1b0;read_data_vld1b0;read_data0;end end endmoduleflash_cmdtimescale1ns/1ps//////////////////////////////////////////////////////////////////////////////////// Company:// Engineer: QSJ//// Create Date: 2021/03/26 9:04:02// Design Name:// Module Name: flash_cmd// Project Name:// Target Devices:// Tool Versions:// Description://// Dependencies://// Revision:// Revision 0.01 - File Created// Additional Comments:////////////////////////////////////////////////////////////////////////////////////moduleflash_cmd(input sys_clk,input i_rst_n,input i_wr_flash_start,input i_rd_flash_start,input i_rd_device_id_start,input i_subsector_erase_start,input wire[7:0]iv_write_data,output wire o_wr_1_byte_ok,input wire[15:0]iv_write_num,input wire[15:0]iv_read_num,input wire[31:0]iv_base_addr,output o_spi_clk,output o_spi_cs,output o_spi_mosi,input i_spi_miso,output[7:0]ov_rd_data,output o_rd_data_vld);reg[7:0]flash_cmd_def;reg[3:0]cmd_type;wire flash_done;wire[7:0]read_data;wire read_data_vld;reg[4:0]curr_stated15;always (posedge sys_clk)beginif(!i_rst_n)begin curr_stated15;flash_cmd_def8d0;cmd_type4b0000;endelsebegincase(curr_state)d0://idleif(i_wr_flash_start)curr_stated8;elseif(i_rd_flash_start)curr_stated13;elseif(i_rd_device_id_start)curr_stated1;elseif(i_subsector_erase_start)curr_stated3;elsecurr_stated0;// -------------- read device ID ------------------d1://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated2;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d2:// Read Device ID:9FHif(flash_done)begin flash_cmd_def8h00;if(read_data8hFF)// if the device id is errorcurr_stated1;elsecurr_stated0;cmd_type4b0000;endelsebegin flash_cmd_def8h9f;curr_statecurr_state;cmd_type4b1000;end// -------------- Erase ------------------d3://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated4;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d4://Write Enable:06Hif(flash_done)begin flash_cmd_def8h00;curr_stated5;cmd_type4b0000;endelsebegin flash_cmd_def8h06;curr_statecurr_state;cmd_type4b1001;end d5://4-byte address mode Sector Erase:DCH Subsector Erase:21Hif(flash_done)begin flash_cmd_def8h00;curr_stated6;cmd_type4b0000;endelsebegin flash_cmd_def8h21;curr_statecurr_state;cmd_type4b1010;end d6://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated7;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d7://Write disable: 04Hif(flash_done)begin flash_cmd_def8h00;curr_stated0;cmd_type4b0000;endelsebegin flash_cmd_def8h04;cmd_type4b1100;end// -------------- write Data ------------------d8://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated9;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d9://Write Enable:06Hif(flash_done)begin flash_cmd_def8h00;curr_stated10;cmd_type4b0000;endelsebegin flash_cmd_def8h06;cmd_type4b1001;end d10://4-byte address page program: write data to flashif(flash_done)begin flash_cmd_def8h00;curr_stated11;cmd_type4b0000;endelsebegin flash_cmd_def8h12;cmd_type4b1101;end d11://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated12;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d12://Write disable: 04Hif(flash_done)begin flash_cmd_def8h00;curr_stated0;cmd_type4b0000;endelsebegin flash_cmd_def8h04;cmd_type4b1100;end// -------------- read Data ------------------d13://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated14;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d14://4-byte address read flash dataif(flash_done)begin flash_cmd_def8h00;curr_stated0;cmd_type4b0000;endelsebegin flash_cmd_def8h13;cmd_type4b1110;end// -------------- enter 4-byte mode ------------------d15://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated16;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d16://Write Enable:06Hif(flash_done)begin flash_cmd_def8h00;curr_stated17;cmd_type4b0000;endelsebegin flash_cmd_def8h06;cmd_type4b1001;end d17://Enter 4-byte address mode:B7Hif(flash_done)begin flash_cmd_def8h00;curr_stated18;cmd_type4b0000;endelsebegin flash_cmd_def8hB7;cmd_type4b1001;end d18://Read Status Register:05Hif(flash_done)beginif(read_data[0]1b0)begin flash_cmd_def8h00;curr_stated19;cmd_type4b0000;endelsebegin flash_cmd_def8h05;cmd_type4b1011;end endelsebegin flash_cmd_def8h05;cmd_type4b1011;end d19://Write disable: 04Hif(flash_done)begin flash_cmd_def8h00;curr_stated1;cmd_type4b0000;endelsebegin flash_cmd_def8h04;cmd_type4b1100;end endcase end end reg[31:0]base_addr;always (posedge sys_clk)beginif(!i_rst_n)begin base_addrd0;endelsebeginif(curr_state0)beginif(i_wr_flash_start|i_rd_flash_start|i_subsector_erase_start)base_addriv_base_addr;elsebase_addrd0;endelsebase_addrbase_addr;end end flash_spiU_flash_spi(.sys_clk(sys_clk),.i_rst_n(i_rst_n),.o_spi_clk(o_spi_clk),.o_spi_cs(o_spi_cs),.o_spi_mosi(o_spi_mosi),.i_spi_miso(i_spi_miso),.iv_write_data(iv_write_data),.o_wr_1_byte_ok(o_wr_1_byte_ok),.iv_write_num(iv_write_num),.iv_read_num(iv_read_num),.iv_cmd_type(cmd_type),.o_flash_done(flash_done),.iv_flash_cmd(flash_cmd_def),.iv_flash_addr(base_addr),.ov_read_data(read_data),.o_read_data_vld(read_data_vld));assign ov_rd_dataread_data;assign o_rd_data_vld(curr_stated14)?read_data_vld:0;endmodule总结以上就是全部内容仅做个人记录若需要对flash进行更多操作可阅读flash对应的datasheet。有完整的VIVADO FPGA测试工程。工程未经过全面的调试有问题请指正