【HDLbits--counter】

题目：基础计数器

module top_module (input clk,input reset,output [9:0] q);always @(posedge clk) beginif(reset) beginq <= 0;end else beginif(q==999) beginq <= 0;end else beginq <= q + 1; endendend
endmodule

题目：

module top_module (input clk,input shift_ena,input count_ena,input data,output [3:0] q);always @(posedge clk) beginif(shift_ena) beginq <= {q[2:0],data};end else beginq <= q - 1'b1; endend
endmodule

题目：

module top_module (input clk,input reset,      // Synchronous resetinput data,output start_shifting);//============================//==Mearly FSM//============================parameter S0 = 3'b000;parameter S1 = 3'b001;parameter S2 = 3'b010;parameter S3 = 3'b100;reg[3 -1:0] cur_sta;reg[3 -1:0] nxt_sta;//==State transitionalways @(*) begincase(cur_sta)S0: nxt_sta = (data==1'b1) ? S1 : S0;S1: nxt_sta = (data==1'b1) ? S2 : S0;S2: nxt_sta = (data==1'b0) ? S3 : S2;S3: nxt_sta = S0;default: nxt_sta = S0;endcaseend//==State D-flop-flopalways @(posedge clk) beginif(reset) begincur_sta <= S0;end else begincur_sta <= nxt_sta; endend//==Output always @(posedge clk) beginif(reset) beginstart_shifting <= 1'b0;end else beginstart_shifting <= ((cur_sta==S3) && (data==1'b1)) ? 1 : start_shifting; endend
endmodule