systemverilog中的unique if

1 基本概念

        在 SystemVerilog 中，unique if是一种条件判断结构。它用于检查多个互斥的条件，以确保在给定的情况下只有一个条件分支被执行。这有助于提高代码的可读性和可维护性，同时也能帮助发现潜在的逻辑错误，报错原因有以下两个

        当所有的 “if” 条件都不匹配时且无else语句，会报错。
        当在 “if-else” 条件中发现有不止一个条件匹配时，会报错。

2 语法

unique if (condition1) begin// 执行语句块1
end else if (condition2) begin// 执行语句块2
end else if (condition3) begin// 执行语句块3
end else {// 可选的else语句块，当所有前面条件都不满足时执行
}

3 示例

1 No else block for unique-if（无else，且都不匹配）

module tb;int x = 4;initial begin// This if else if construct is declared to be "unique"// Error is not reported here because there is a "else"// clause in the end which will be triggered when none of// the conditions matchunique if (x == 3)$display ("x is %0d", x);else if (x == 5)$display ("x is %0d", x);else$display ("x is neither 3 nor 5");// When none of the conditions become true and there// is no "else" clause, then an error is reportedunique if (x == 3)$display ("x is %0d", x);else if (x == 5)$display ("x is %0d", x);end
endmodule//------------- simulation log-------------------//
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Unique if violation:  Every if clause was false.File: ./testbench.sv, line = 18, pos = 13Scope: tbTime: 0 FS + 1ncsim: *W,RNQUIE: Simulation is complete.

2 Multiple matches in unique-if（匹配多次）

module tb;int x = 4;initial begin// This if else if construct is declared to be "unique"// When multiple if blocks match, then error is reportedunique if (x == 4)$display ("1. x is %0d", x);else if (x == 4)$display ("2. x is %0d", x);else$display ("x is not 4");end
endmodule//--------------- simulation log-----------------//
ncsim> run
1. x is 4
ncsim: *W,MCONDE: Unique if violation:  Multiple true if clauses at {line=8:pos=15 and line=10:pos=13}.File: ./testbench.sv, line = 8, pos = 15Scope: tbTime: 0 FS + 1ncsim: *W,RNQUIE: Simulation is complete.

https://www.chipverify.com/systemverilog/systemverilog-unique-priority-if-ele