FPGA 综合笔记

仿真时阻塞赋值和非阻塞赋值

Use of Non-Blocking Assignment in Testbench : Verilog

Use of Non-Blocking Assignment in Testbench : Verilog - Stack Overflow

non-blocking assignment does not work as expected in Verilog

non-blocking assignment does not work as expected in Verilog - Electrical Engineering Stack Exchange

This is actually quite similar to a question I answered previously, but I will try to build up a canonical answer for this somewhat common issue.

In a zero-delay simulation like this, the test flip-flop has a setup time and a hold time of zero:

```math

Tsetup=Thold=0

```

What this means is that the instant the sensitive clock edge occurs, the output is updated, regardless of what happened immediately before or after that instant. This is not like real hardware which would usually have a non-zero 𝑇𝑠𝑒𝑡𝑢𝑝 and 𝑇ℎ𝑜𝑙𝑑.

I ran your testbench, and the results are pretty clear. The valid signal changes at the same time the clock signal does. You have delayed them by precisely the same amount. So at the very edge when the clock is high, the valid signal has also changed:

Both the input (div_valid), and the clock (gclk) go high at the same time: 220 ns. Therefore, the DFF latches this new data, and the output changes instantly since there is also 0 propagation delay. This simulation would look less confusing if we just chose a different delay value for the input to the design:

In this case, we update the input on the falling edge of the clock (620 ns). It is much more clear now that the next clock edge (640 ns) will be when the DFF updates its output.

Curious state transitions in state machine RTL simulation

digital logic - Curious state transitions in state machine RTL simulation - Electrical Engineering Stack Exchange

Pitfall: If your testbench updates the TxSync input exactly at the rising clock edge, You will just have a glitch in nextState. Your simulator may remove this glitch, making it look like nextState never entered State_WRITETOLANE1, when in fact it did, just for a very brief moment. This would make it look like currentState latched a value that nextState never had.

Remedy: Don't update the inputs exactly at the rising clock edge. Add some small delay so that the simulation can be more clearly understood. In my case, I updated the input at the falling clock edge. But the update time is arbitrary if you are doing a 0 delay simulation.

陷阱：如果您的测试台在上升的时钟边缘精确更新了 TxSync 输入，那么 nextState 中将会出现一个毛刺。您的模拟器可能会消除这个毛刺，使其看起来 nextState 从未进入过 State_WRITETOLANE1 状态，但实际上它确实进入过，只是非常短暂。这会让它看起来 currentState 捕获了一个 nextState 从未拥有的值。

解决方法：不要在上升的时钟边缘精确更新输入。增加一些小延迟，以便模拟更清晰地理解。在我的情况下，我是在下降的时钟边缘更新输入的。但如果您正在进行零延迟模拟，更新时间是任意的。

Quartus 编译错误

Can't place multiple pins assigned to pin location

Error (176310): Can't place multiple pins assigned to pin location Pin_101 (IOPAD_X34_Y18_N21) Info (176311): Pin ch1_dac[3] is assigned to pin location Pin_101 (IOPAD_X34_Y18_N21) Info (176311): Pin ALTERA_nCEO is assigned to pin location Pin_101 (IOPAD_X34_Y18_N21)

解决办法：

菜单->Assignments->Device->Device and Pin Options:

将相关引脚改为普通 IO:

仿真通过，上板验证失败

解决办法：板子断电，上电，再烧录

一个可能的原因：FPGA 器件支持除法吗？

固化程序启动失败

故障描述

EP4CE6E22C8 通过 jic 文件固化成功，但是启动失败，FPGA 的 CONF_DONE 引脚输出总是低。实际该引脚在配置期间为低，配置成功后为高。

启动失败板子：带10k 上电阻，CONIFG_DONE 脚对地95M电阻，对VCC电阻：32k

启动 OK 的板子：CONFIG_DONE 脚对比：102M,， 对 VCC电阻：102M

故障原因

怀疑1：板子 FPGA 引脚有四根分线，怀疑是飞线过多，在操作时烧了板子。

怀疑2： CONF_DONE 引脚的 R27、D1 是手焊的，可能在焊接时烧了板子？

尝试

测量 FPGA 晶振频率： OK

尝试重新焊接 R19 ，失败

尝试更换 W25Q16: 失败

尝试重新编译: 失败

FPGA 坏了，只能更换FPGA