Verilog：写流水灯时遇到的问题

module flow_led(input 		sys_clk, //系统时钟50Mhz 周期0.02nsinput 		sys_rst_n, //系统异步复位，低电平有效output reg [3:0] led
);
reg [24:0] cnt;//计数器计时0.5s=250000000*0.02ns
always@(posedge sys_clk or negedge sys_rst_n)beginif(!sys_rst_n)cnt <= 25'd0;//else if(cnt < (25'd250000000 - 25'd1))else if(cnt < (25'd25 - 25'd1))cnt <= cnt + 25'd1;elsecnt <= 25'd0;
end//LED移位控制
always@(posedge sys_clk or negedge sys_rst_n)beginif(!sys_rst_n)led <= 4'b0001;//else if(cnt == (25'd250000000 - 25'd1))else if(cnt == (25'd25 - 25'd1))led <= {led[2:0],led[3]}; 
endendmodule

在写LED移位控制部分的代码时

为什么always里的判断是posedge sys_clk or negedge sys_rst_n呢？

用*在modelsim里会报错：Iteration limit 10000000 reached 

用*为什么不可以呢？