Verilog中的： `+:` 和 `-:`

+: 和 -:

标准解释

logic [15:0] down_vect;
logic [0:15] up_vect;down_vect[lsb_base_expr +: width_expr]
up_vect  [msb_base_expr +: width_expr]
down_vect[msb_base_expr -: width_expr]
up_vect  [lsb_base_expr -: width_expr]

举例

reg [31:0] dword;
reg [7:0] byte0;
reg [7:0] byte1;
reg [7:0] byte2;
reg [7:0] byte3;assign byte0 = dword[0 +: 8];    // Same as dword[7:0]
assign byte1 = dword[8 +: 8];    // Same as dword[15:8]
assign byte2 = dword[16 +: 8];   // Same as dword[23:16]
assign byte3 = dword[24 +: 8];   // Same as dword[31:24]

练习题

assign rx_data0_i = { ad_dout_w[0*6 +: 6] ,  ad_dout_w[2*6 +: 6] };
assign rx_data0_q = { ad_dout_w[1*6 +: 6] ,  ad_dout_w[3*6 +: 6] };  
assign rx_data1_i = { ad_dout_w[4*6 +: 6] ,  ad_dout_w[6*6 +: 6] };  
assign rx_data1_q = { ad_dout_w[5*6 +: 6] ,  ad_dout_w[7*6 +: 6] }; assign rx_data0_i = { ad_dout_w[  5 : 0] ,  ad_dout_w[ 17 :12] };
assign rx_data0_q = { ad_dout_w[ 11 : 6] ,  ad_dout_w[ 23 :18] };  
assign rx_data1_i = { ad_dout_w[ 29 :24] ,  ad_dout_w[ 41 :36] };  
assign rx_data1_q = { ad_dout_w[ 35 :30] ,  ad_dout_w[ 47 :42] };