使用Keil V6编译 FreeRTOS CMSIS V2版本 ETH + Lwip 编译报错问题解决方式

网上其他人写的都解决不了，要不用的是CMSIS V1版本，根据他们的方式搞完还是报错，今天花点时间自己搞一下。

不想自己动手？没问题，模版已上传Gitee

https://gitee.com/maybe_404/stm32-f4xx_-free-rtos_-lwip_-template.git

1、HAL库版本：最新版V1.28.1

2、FreeRTOS版本：CMSIS V2接口 10.3.1

3、Lwip协议栈版本：2.1.2

4、使用CUBEMX生产后，使用Keil V6编译

编译报错251

5、编译报错问题解决

第一步、Lwip报错问题解决方式：见我另一篇文章

第二步、把CMSIS编译器的.C文件改一下（不好找的话直接去项目文件夹里搜索 cmsis_compiler.h）

内容直接全删了，使用下面的代码

/**************************************************************************//*** @file     cmsis_compiler.h* @brief    CMSIS compiler generic header file* @version  V5.1.0* @date     09. October 2018******************************************************************************/
/** Copyright (c) 2009-2018 Arm Limited. All rights reserved.** SPDX-License-Identifier: Apache-2.0** Licensed under the Apache License, Version 2.0 (the License); you may* not use this file except in compliance with the License.* You may obtain a copy of the License at** www.apache.org/licenses/LICENSE-2.0** Unless required by applicable law or agreed to in writing, software* distributed under the License is distributed on an AS IS BASIS, WITHOUT* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.* See the License for the specific language governing permissions and* limitations under the License.*/#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H#include <stdint.h>#include "cmsis_armclang.h"       //其它全删，没屌用#endif /* __CMSIS_COMPILER_H */

第三步、FreeRTOS 报错问题解决

第一种方式、复制CubeMX pack包中的(一般在C:\Users\xxxxx你的电脑用户名\STM32Cube\Repository\STM32Cube_FW_F4_V1.28.1\Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F)GCC版本的port.c 和 portmacro.h到

当前项目

第二种方式、懒得找的话，直接用下面源码重写这两文件。

port.c

/** FreeRTOS Kernel V10.3.1* Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.** Permission is hereby granted, free of charge, to any person obtaining a copy of* this software and associated documentation files (the "Software"), to deal in* the Software without restriction, including without limitation the rights to* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of* the Software, and to permit persons to whom the Software is furnished to do so,* subject to the following conditions:** The above copyright notice and this permission notice shall be included in all* copies or substantial portions of the Software.** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.** http://www.FreeRTOS.org* http://aws.amazon.com/freertos** 1 tab == 4 spaces!*//*-----------------------------------------------------------* Implementation of functions defined in portable.h for the ARM CM4F port.*----------------------------------------------------------*//* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"#ifndef __VFP_FP__#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif#ifndef configSYSTICK_CLOCK_HZ#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ/* Ensure the SysTick is clocked at the same frequency as the core. */#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
#else/* The way the SysTick is clocked is not modified in case it is not the sameas the core. */#define portNVIC_SYSTICK_CLK_BIT	( 0 )
#endif/* Constants required to manipulate the core.  Registers first... */
#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
r0p1 port. */
#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
#define portPRIGROUP_SHIFT					( 8UL )/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
#define portVECTACTIVE_MASK					( 0xFFUL )/* Constants required to manipulate the VFP. */
#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR					( 0x01000000 )
#define portINITIAL_EXC_RETURN				( 0xfffffffd )/* The systick is a 24-bit counter. */
#define portMAX_24_BIT_NUMBER				( 0xffffffUL )/* For strict compliance with the Cortex-M spec the task start address should
have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )/* A fiddle factor to estimate the number of SysTick counts that would have
occurred while the SysTick counter is stopped during tickless idle
calculations. */
#define portMISSED_COUNTS_FACTOR			( 45UL )/* Let the user override the pre-loading of the initial LR with the address of
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
#ifdef configTASK_RETURN_ADDRESS#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
#else#define portTASK_RETURN_ADDRESS	prvTaskExitError
#endif/** Setup the timer to generate the tick interrupts.  The implementation in this* file is weak to allow application writers to change the timer used to* generate the tick interrupt.*/
void vPortSetupTimerInterrupt( void );/** Exception handlers.*/
void xPortPendSVHandler( void ) __attribute__ (( naked ));
void xPortSysTickHandler( void );
void vPortSVCHandler( void ) __attribute__ (( naked ));/** Start first task is a separate function so it can be tested in isolation.*/
static void prvPortStartFirstTask( void ) __attribute__ (( naked ));/** Function to enable the VFP.*/
static void vPortEnableVFP( void ) __attribute__ (( naked ));/** Used to catch tasks that attempt to return from their implementing function.*/
static void prvTaskExitError( void );/*-----------------------------------------------------------*//* Each task maintains its own interrupt status in the critical nesting
variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;/** The number of SysTick increments that make up one tick period.*/
#if( configUSE_TICKLESS_IDLE == 1 )static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE *//** The maximum number of tick periods that can be suppressed is limited by the* 24 bit resolution of the SysTick timer.*/
#if( configUSE_TICKLESS_IDLE == 1 )static uint32_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE *//** Compensate for the CPU cycles that pass while the SysTick is stopped (low* power functionality only.*/
#if( configUSE_TICKLESS_IDLE == 1 )static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE *//** Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure* FreeRTOS API functions are not called from interrupts that have been assigned* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.*/
#if( configASSERT_DEFINED == 1 )static uint8_t ucMaxSysCallPriority = 0;static uint32_t ulMaxPRIGROUPValue = 0;static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED *//*-----------------------------------------------------------*//** See header file for description.*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{/* Simulate the stack frame as it would be created by a context switchinterrupt. *//* Offset added to account for the way the MCU uses the stack on entry/exitof interrupts, and to ensure alignment. */pxTopOfStack--;*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */pxTopOfStack--;*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */pxTopOfStack--;*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR *//* Save code space by skipping register initialisation. */pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 *//* A save method is being used that requires each task to maintain itsown exec return value. */pxTopOfStack--;*pxTopOfStack = portINITIAL_EXC_RETURN;pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */return pxTopOfStack;
}
/*-----------------------------------------------------------*/static void prvTaskExitError( void )
{
volatile uint32_t ulDummy = 0;/* A function that implements a task must not exit or attempt to return toits caller as there is nothing to return to.  If a task wants to exit itshould instead call vTaskDelete( NULL ).Artificially force an assert() to be triggered if configASSERT() isdefined, then stop here so application writers can catch the error. */configASSERT( uxCriticalNesting == ~0UL );portDISABLE_INTERRUPTS();while( ulDummy == 0 ){/* This file calls prvTaskExitError() after the scheduler has beenstarted to remove a compiler warning about the function being definedbut never called.  ulDummy is used purely to quieten other warningsabout code appearing after this function is called - making ulDummyvolatile makes the compiler think the function could return andtherefore not output an 'unreachable code' warning for code that appearsafter it. */}
}
/*-----------------------------------------------------------*/void vPortSVCHandler( void )
{__asm volatile ("	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */"	msr psp, r0						\n" /* Restore the task stack pointer. */"	isb								\n""	mov r0, #0 						\n""	msr	basepri, r0					\n""	bx r14							\n""									\n""	.align 4						\n""pxCurrentTCBConst2: .word pxCurrentTCB				\n");
}
/*-----------------------------------------------------------*/static void prvPortStartFirstTask( void )
{/* Start the first task.  This also clears the bit that indicates the FPU isin use in case the FPU was used before the scheduler was started - whichwould otherwise result in the unnecessary leaving of space in the SVC stackfor lazy saving of FPU registers. */__asm volatile(" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */" ldr r0, [r0] 			\n"" ldr r0, [r0] 			\n"" msr msp, r0			\n" /* Set the msp back to the start of the stack. */" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */" msr control, r0		\n"" cpsie i				\n" /* Globally enable interrupts. */" cpsie f				\n"" dsb					\n"" isb					\n"" svc 0					\n" /* System call to start first task. */" nop					\n");
}
/*-----------------------------------------------------------*//** See header file for description.*/
BaseType_t xPortStartScheduler( void )
{/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );/* This port can be used on all revisions of the Cortex-M7 core other thanthe r0p1 parts.  r0p1 parts should use the port from the/source/portable/GCC/ARM_CM7/r0p1 directory. */configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );#if( configASSERT_DEFINED == 1 ){volatile uint32_t ulOriginalPriority;volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );volatile uint8_t ucMaxPriorityValue;/* Determine the maximum priority from which ISR safe FreeRTOS APIfunctions can be called.  ISR safe functions are those that end in"FromISR".  FreeRTOS maintains separate thread and ISR API functions toensure interrupt entry is as fast and simple as possible.Save the interrupt priority value that is about to be clobbered. */ulOriginalPriority = *pucFirstUserPriorityRegister;/* Determine the number of priority bits available.  First write to allpossible bits. */*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;/* Read the value back to see how many bits stuck. */ucMaxPriorityValue = *pucFirstUserPriorityRegister;/* Use the same mask on the maximum system call priority. */ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;/* Calculate the maximum acceptable priority group value for the numberof bits read back. */ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ){ulMaxPRIGROUPValue--;ucMaxPriorityValue <<= ( uint8_t ) 0x01;}#ifdef __NVIC_PRIO_BITS{/* Check the CMSIS configuration that defines the number ofpriority bits matches the number of priority bits actually queriedfrom the hardware. */configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );}#endif#ifdef configPRIO_BITS{/* Check the FreeRTOS configuration that defines the number ofpriority bits matches the number of priority bits actually queriedfrom the hardware. */configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );}#endif/* Shift the priority group value back to its position within the AIRCRregister. */ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;/* Restore the clobbered interrupt priority register to its originalvalue. */*pucFirstUserPriorityRegister = ulOriginalPriority;}#endif /* conifgASSERT_DEFINED *//* Make PendSV and SysTick the lowest priority interrupts. */portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;/* Start the timer that generates the tick ISR.  Interrupts are disabledhere already. */vPortSetupTimerInterrupt();/* Initialise the critical nesting count ready for the first task. */uxCriticalNesting = 0;/* Ensure the VFP is enabled - it should be anyway. */vPortEnableVFP();/* Lazy save always. */*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;/* Start the first task. */prvPortStartFirstTask();/* Should never get here as the tasks will now be executing!  Call the taskexit error function to prevent compiler warnings about a static functionnot being called in the case that the application writer overrides thisfunctionality by defining configTASK_RETURN_ADDRESS.  CallvTaskSwitchContext() so link time optimisation does not remove thesymbol. */vTaskSwitchContext();prvTaskExitError();/* Should not get here! */return 0;
}
/*-----------------------------------------------------------*/void vPortEndScheduler( void )
{/* Not implemented in ports where there is nothing to return to.Artificially force an assert. */configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/void vPortEnterCritical( void )
{portDISABLE_INTERRUPTS();uxCriticalNesting++;/* This is not the interrupt safe version of the enter critical function soassert() if it is being called from an interrupt context.  Only APIfunctions that end in "FromISR" can be used in an interrupt.  Only assert ifthe critical nesting count is 1 to protect against recursive calls if theassert function also uses a critical section. */if( uxCriticalNesting == 1 ){configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );}
}
/*-----------------------------------------------------------*/void vPortExitCritical( void )
{configASSERT( uxCriticalNesting );uxCriticalNesting--;if( uxCriticalNesting == 0 ){portENABLE_INTERRUPTS();}
}
/*-----------------------------------------------------------*/void xPortPendSVHandler( void )
{/* This is a naked function. */__asm volatile("	mrs r0, psp							\n""	isb									\n""										\n""	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */"	ldr	r2, [r3]						\n""										\n""	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */"	it eq								\n""	vstmdbeq r0!, {s16-s31}				\n""										\n""	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */"										\n""	stmdb sp!, {r0, r3}					\n""	mov r0, %0 							\n""	msr basepri, r0						\n""	dsb									\n""	isb									\n""	bl vTaskSwitchContext				\n""	mov r0, #0							\n""	msr basepri, r0						\n""	ldmia sp!, {r0, r3}					\n""										\n""	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */"	ldr r0, [r1]						\n""										\n""	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */"										\n""	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */"	it eq								\n""	vldmiaeq r0!, {s16-s31}				\n""										\n""	msr psp, r0							\n""	isb									\n""										\n"#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */#if WORKAROUND_PMU_CM001 == 1"			push { r14 }				\n""			pop { pc }					\n"#endif#endif"										\n""	bx r14								\n""										\n""	.align 4							\n""pxCurrentTCBConst: .word pxCurrentTCB	\n"::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY));
}
/*-----------------------------------------------------------*/void xPortSysTickHandler( void )
{/* The SysTick runs at the lowest interrupt priority, so when this interruptexecutes all interrupts must be unmasked.  There is therefore no need tosave and then restore the interrupt mask value as its value is alreadyknown. */portDISABLE_INTERRUPTS();{/* Increment the RTOS tick. */if( xTaskIncrementTick() != pdFALSE ){/* A context switch is required.  Context switching is performed inthe PendSV interrupt.  Pend the PendSV interrupt. */portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;}}portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/#if( configUSE_TICKLESS_IDLE == 1 )__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ){uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;TickType_t xModifiableIdleTime;/* Make sure the SysTick reload value does not overflow the counter. */if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ){xExpectedIdleTime = xMaximumPossibleSuppressedTicks;}/* Stop the SysTick momentarily.  The time the SysTick is stopped foris accounted for as best it can be, but using the tickless mode willinevitably result in some tiny drift of the time maintained by thekernel with respect to calendar time. */portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;/* Calculate the reload value required to wait xExpectedIdleTimetick periods.  -1 is used because this code will execute part waythrough one of the tick periods. */ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );if( ulReloadValue > ulStoppedTimerCompensation ){ulReloadValue -= ulStoppedTimerCompensation;}/* Enter a critical section but don't use the taskENTER_CRITICAL()method as that will mask interrupts that should exit sleep mode. */__asm volatile( "cpsid i" ::: "memory" );__asm volatile( "dsb" );__asm volatile( "isb" );/* If a context switch is pending or a task is waiting for the schedulerto be unsuspended then abandon the low power entry. */if( eTaskConfirmSleepModeStatus() == eAbortSleep ){/* Restart from whatever is left in the count register to completethis tick period. */portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;/* Restart SysTick. */portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;/* Reset the reload register to the value required for normal tickperiods. */portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;/* Re-enable interrupts - see comments above the cpsid instruction()above. */__asm volatile( "cpsie i" ::: "memory" );}else{/* Set the new reload value. */portNVIC_SYSTICK_LOAD_REG = ulReloadValue;/* Clear the SysTick count flag and set the count value back tozero. */portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;/* Restart SysTick. */portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() canset its parameter to 0 to indicate that its implementation containsits own wait for interrupt or wait for event instruction, and so wfishould not be executed again.  However, the original expected idletime variable must remain unmodified, so a copy is taken. */xModifiableIdleTime = xExpectedIdleTime;configPRE_SLEEP_PROCESSING( xModifiableIdleTime );if( xModifiableIdleTime > 0 ){__asm volatile( "dsb" ::: "memory" );__asm volatile( "wfi" );__asm volatile( "isb" );}configPOST_SLEEP_PROCESSING( xExpectedIdleTime );/* Re-enable interrupts to allow the interrupt that brought the MCUout of sleep mode to execute immediately.  see comments above__disable_interrupt() call above. */__asm volatile( "cpsie i" ::: "memory" );__asm volatile( "dsb" );__asm volatile( "isb" );/* Disable interrupts again because the clock is about to be stoppedand interrupts that execute while the clock is stopped will increaseany slippage between the time maintained by the RTOS and calendartime. */__asm volatile( "cpsid i" ::: "memory" );__asm volatile( "dsb" );__asm volatile( "isb" );/* Disable the SysTick clock without reading theportNVIC_SYSTICK_CTRL_REG register to ensure theportNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,the time the SysTick is stopped for is accounted for as best it canbe, but using the tickless mode will inevitably result in some tinydrift of the time maintained by the kernel with respect to calendartime*/portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );/* Determine if the SysTick clock has already counted to zero andbeen set back to the current reload value (the reload back beingcorrect for the entire expected idle time) or if the SysTick is yetto count to zero (in which case an interrupt other than the SysTickmust have brought the system out of sleep mode). */if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ){uint32_t ulCalculatedLoadValue;/* The tick interrupt is already pending, and the SysTick countreloaded with ulReloadValue.  Reset theportNVIC_SYSTICK_LOAD_REG with whatever remains of this tickperiod. */ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );/* Don't allow a tiny value, or values that have somehowunderflowed because the post sleep hook did somethingthat took too long. */if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ){ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );}portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;/* As the pending tick will be processed as soon as thisfunction exits, the tick value maintained by the tick is steppedforward by one less than the time spent waiting. */ulCompleteTickPeriods = xExpectedIdleTime - 1UL;}else{/* Something other than the tick interrupt ended the sleep.Work out how long the sleep lasted rounded to complete tickperiods (not the ulReload value which accounted for partticks). */ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;/* How many complete tick periods passed while the processorwas waiting? */ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;/* The reload value is set to whatever fraction of a single tickperiod remains. */portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;}/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REGagain, then set portNVIC_SYSTICK_LOAD_REG back to its standardvalue. */portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;vTaskStepTick( ulCompleteTickPeriods );portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;/* Exit with interrupts enabled. */__asm volatile( "cpsie i" ::: "memory" );}}#endif /* #if configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*//** Setup the systick timer to generate the tick interrupts at the required* frequency.*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{/* Calculate the constants required to configure the tick interrupt. */#if( configUSE_TICKLESS_IDLE == 1 ){ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );}#endif /* configUSE_TICKLESS_IDLE *//* Stop and clear the SysTick. */portNVIC_SYSTICK_CTRL_REG = 0UL;portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;/* Configure SysTick to interrupt at the requested rate. */portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*//* This is a naked function. */
static void vPortEnableVFP( void )
{__asm volatile("	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */"	ldr r1, [r0]				\n""								\n""	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */"	str r1, [r0]				\n""	bx r14						");
}
/*-----------------------------------------------------------*/#if( configASSERT_DEFINED == 1 )void vPortValidateInterruptPriority( void ){uint32_t ulCurrentInterrupt;uint8_t ucCurrentPriority;/* Obtain the number of the currently executing interrupt. */__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );/* Is the interrupt number a user defined interrupt? */if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ){/* Look up the interrupt's priority. */ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];/* The following assertion will fail if a service routine (ISR) foran interrupt that has been assigned a priority aboveconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS APIfunction.  ISR safe FreeRTOS API functions must *only* be calledfrom interrupts that have been assigned a priority at or belowconfigMAX_SYSCALL_INTERRUPT_PRIORITY.Numerically low interrupt priority numbers represent logically highinterrupt priorities, therefore the priority of the interrupt mustbe set to a value equal to or numerically *higher* thanconfigMAX_SYSCALL_INTERRUPT_PRIORITY.Interrupts that	use the FreeRTOS API must not be left at theirdefault priority of	zero as that is the highest possible priority,which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,and	therefore also guaranteed to be invalid.FreeRTOS maintains separate thread and ISR API functions to ensureinterrupt entry is as fast and simple as possible.The following links provide detailed information:http://www.freertos.org/RTOS-Cortex-M3-M4.htmlhttp://www.freertos.org/FAQHelp.html */configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );}/* Priority grouping:  The interrupt controller (NVIC) allows the bitsthat define each interrupt's priority to be split between bits thatdefine the interrupt's pre-emption priority bits and bits that definethe interrupt's sub-priority.  For simplicity all bits must be definedto be pre-emption priority bits.  The following assertion will fail ifthis is not the case (if some bits represent a sub-priority).If the application only uses CMSIS libraries for interruptconfiguration then the correct setting can be achieved on all Cortex-Mdevices by calling NVIC_SetPriorityGrouping( 0 ); before starting thescheduler.  Note however that some vendor specific peripheral librariesassume a non-zero priority group setting, in which cases using a valueof zero will result in unpredictable behaviour. */configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );}#endif /* configASSERT_DEFINED */

portmacro.h

/** FreeRTOS Kernel V10.3.1* Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.** Permission is hereby granted, free of charge, to any person obtaining a copy of* this software and associated documentation files (the "Software"), to deal in* the Software without restriction, including without limitation the rights to* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of* the Software, and to permit persons to whom the Software is furnished to do so,* subject to the following conditions:** The above copyright notice and this permission notice shall be included in all* copies or substantial portions of the Software.** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.** http://www.FreeRTOS.org* http://aws.amazon.com/freertos** 1 tab == 4 spaces!*/#ifndef PORTMACRO_H
#define PORTMACRO_H#ifdef __cplusplus
extern "C" {
#endif/*-----------------------------------------------------------* Port specific definitions.** The settings in this file configure FreeRTOS correctly for the* given hardware and compiler.** These settings should not be altered.*-----------------------------------------------------------*//* Type definitions. */
#define portCHAR		char
#define portFLOAT		float
#define portDOUBLE		double
#define portLONG		long
#define portSHORT		short
#define portSTACK_TYPE	uint32_t
#define portBASE_TYPE	longtypedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;#if( configUSE_16_BIT_TICKS == 1 )typedef uint16_t TickType_t;#define portMAX_DELAY ( TickType_t ) 0xffff
#elsetypedef uint32_t TickType_t;#define portMAX_DELAY ( TickType_t ) 0xffffffffUL/* 32-bit tick type on a 32-bit architecture, so reads of the tick count donot need to be guarded with a critical section. */#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*//* Architecture specifics. */
#define portSTACK_GROWTH			( -1 )
#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT			8
/*-----------------------------------------------------------*//* Scheduler utilities. */
#define portYIELD() 															\
{																				\/* Set a PendSV to request a context switch. */								\portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\\/* Barriers are normally not required but do ensure the code is completely	\within the specified behaviour for the architecture. */						\__asm volatile( "dsb" ::: "memory" );										\__asm volatile( "isb" );													\
}#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*//* Critical section management. */
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
#define portENTER_CRITICAL()					vPortEnterCritical()
#define portEXIT_CRITICAL()						vPortExitCritical()/*-----------------------------------------------------------*//* Task function macros as described on the FreeRTOS.org WEB site.  These are
not necessary for to use this port.  They are defined so the common demo files
(which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*//* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEPextern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
#endif
/*-----------------------------------------------------------*//* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1/* Generic helper function. */__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ){uint8_t ucReturn;__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );return ucReturn;}/* Check the configuration. */#if( configMAX_PRIORITIES > 32 )#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.#endif/* Store/clear the ready priorities in a bit map. */#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )/*-----------------------------------------------------------*/#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION *//*-----------------------------------------------------------*/#ifdef configASSERTvoid vPortValidateInterruptPriority( void );#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
#endif/* portNOP() is not required by this port. */
#define portNOP()#define portINLINE	__inline#ifndef portFORCE_INLINE#define portFORCE_INLINE inline __attribute__(( always_inline))
#endifportFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;/* Obtain the number of the currently executing interrupt. */__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );if( ulCurrentInterrupt == 0 ){xReturn = pdFALSE;}else{xReturn = pdTRUE;}return xReturn;
}/*-----------------------------------------------------------*/portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;__asm volatile("	mov %0, %1												\n"	\"	msr basepri, %0											\n" \"	isb														\n" \"	dsb														\n" \:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory");
}/*-----------------------------------------------------------*/portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;__asm volatile("	mrs %0, basepri											\n" \"	mov %1, %2												\n"	\"	msr basepri, %1											\n" \"	isb														\n" \"	dsb														\n" \:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory");/* This return will not be reached but is necessary to prevent compilerwarnings. */return ulOriginalBASEPRI;
}
/*-----------------------------------------------------------*/portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{__asm volatile("	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory");
}
/*-----------------------------------------------------------*/#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )#ifdef __cplusplus
}
#endif#endif /* PORTMACRO_H */

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