systemverilog中的priority if

1 基本概念

        在 SystemVerilog 中，priority - if是一种条件判断结构。它和普通的if - else语句类似，但在条件评估和错误检查方面有自己的特点，主要用于按顺序评估多个条件，并且对不符合预期的情况进行报错。报错如下两点

        当所有条件都不为真时，

        或者如果最后一个 “if” 结构没有 “else” 子句时。

2 语法结构

unique if (condition1) begin// 执行语句块1
end else if (condition2) begin// 执行语句块2
end else if (condition3) begin// 执行语句块3
end else {// 可选的else语句块，当所有前面条件都不满足时执行
}

3 示例

1 No else clause in priority-if（没有else）

module tb;int x = 4;initial begin// This if else if construct is declared to be "unique"// Error is not reported here because there is a "else"// clause in the end which will be triggered when none of// the conditions matchpriority if (x == 3)$display ("x is %0d", x);else if (x == 5)$display ("x is %0d", x);else$display ("x is neither 3 nor 5");// When none of the conditions become true and there// is no "else" clause, then an error is reportedpriority if (x == 3)$display ("x is %0d", x);else if (x == 5)$display ("x is %0d", x);end
endmodule//----------------- simulation log-----------------//
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Priority if violation:  Every if clause was false.File: ./testbench.sv, line = 18, pos = 15Scope: tbTime: 0 FS + 1ncsim: *W,RNQUIE: Simulation is complete.

2 Multiple matches in unique-if（匹配多个if）

module tb;int x = 4;initial begin// This if else if construct is declared to be "unique"// When multiple if blocks match, then error is reportedpriority if (x == 4)$display ("1. x is %0d", x);else if (x == 4)$display ("2. x is %0d", x);else$display ("x is not 4");end
endmodule//----------------- simulation log-----------------//
ncsim> run
1. x is 4
ncsim: *W,MCONDE: priority if violation:  Multiple true if clauses at {line=8:pos=15 and line=10:pos=13}.File: ./testbench.sv, line = 8, pos = 15Scope: tbTime: 0 FS + 1ncsim: *W,RNQUIE: Simulation is complete.