【数字IC/FPGA】Verilog中的递归调用

参考文章
在Verilog2001中，模块的递归调用是可能的，引用下面的一段话（出自上面的参考文章）

Many designers think that recursive techniques cannot be applied to hardware design. I’m not really sure where this misconception comes from. While it is true that in Verilog ’95 you could not use recursion because the language did not support it, with Verilog 2001, recursion is possible. Recursion is really useful for describing hardware that has a tree structure. Let’s use a priority encoder as an example.

下面，我们将以加法树和find first one两个例子为例，说明模块递归调用在设计电路时的用法。

加法树

由于加法树比较常见，因此这里直接给出设计代码：

module adder
#(parameter